1. Field of the Invention
The present invention relates to a memory device and a semiconductor device including the memory device.
2. Description of the Related Art
Central processing units (CPUs) have a variety of architecture depending on their usage, and architecture called stored-program architecture is predominant architecture of current CPUs. In a stored-program CPU, an instruction and data needed for carrying out the instruction are stored in a semiconductor memory device (hereinafter, simply referred to as a memory device), and the instruction and the data are sequentially read from the memory device, whereby the instruction is carried out.
As the memory device, besides a main memory device for storing data and instructions, a buffer memory device called a cache which can perform data writing and data reading at high speed is given. In order to reduce low-speed access to the main memory device and speed up the arithmetic processing, a cache is provided in a CPU to be located between an arithmetic unit or a control unit and a main memory device. In general, a static random access memory (SRAM) or the like is used as a cache. Patent Document 1 shown below discloses a structure in which a volatile memory such as an SRAM and a nonvolatile memory are used in combination as a cache.